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1. 发明授权

US06263476B1 Method and apparatus for selecting targeted components in limited access test 失效
标题翻译：用于在有限访问测试中选择目标组件的方法和装置
公开(公告)号：US06263476B1
公开(公告)日：2001-07-17
申请号：US09169777
申请日：1998-10-09
申请人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid , Kay C. Lannen
发明人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid , Kay C. Lannen
IPC分类号： G06F1750
CPC分类号： G01R31/27
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

2. 发明授权

US06467051B1 Method and apparatus for selecting test point nodes of a group of components having both accessible and inaccessible nodes for limited access circuit test 失效
标题翻译：用于选择具有可访问和不可访问节点的一组组件的测试点节点用于受限访问电路测试的方法和装置
公开(公告)号：US06467051B1
公开(公告)日：2002-10-15
申请号：US09169421
申请日：1998-10-09
申请人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid , Kay C. Lannen
发明人： Rodney A. Browen , Cherif Ahrikencheikh , William P. Darbie , John E. McDermid , Kay C. Lannen
IPC分类号： G06F1338
CPC分类号： G01R31/318502
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

3. 发明授权

US06334100B1 Method and apparatus for electronic circuit model correction 失效
标题翻译：电子电路模型校正的方法和装置
公开(公告)号：US06334100B1
公开(公告)日：2001-12-25
申请号：US09169502
申请日：1998-10-09
申请人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , Kay C. Lannen , John E. McDermid , Jamie P. Romero
发明人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , Kay C. Lannen , John E. McDermid , Jamie P. Romero
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G01R31/2837
摘要： A method for evaluating and correcting a model of an electronic circuit. A list is created which comprises the minimum number of components that must be specified by the operator in order to be able to compute values for the remaining circuit components. Correction of circuit models can be performed even in cases of limited accessibility to the circuit's nodes.
摘要翻译：一种用于评估和校正电子电路模型的方法。创建列表，其包括操作者必须指定的最小数量的组件，以便能够计算剩余电路组件的值。即使在对电路节点的可访问性有限的情况下也可以进行电路模型的校正。

4. 发明授权

US5412575A Pay-per-use access to multiple electronic test capabilities 失效
标题翻译：按需付费使用多种电子测试功能
公开(公告)号：US5412575A
公开(公告)日：1995-05-02
申请号：US132987
申请日：1993-10-07
申请人： Amanda L. Constant , David W. Webb , Katherine Z. Withers-Miklos , Kay C. Lannen , Ted T. Turner , Amos Hong-Kiat Leong
发明人： Amanda L. Constant , David W. Webb , Katherine Z. Withers-Miklos , Kay C. Lannen , Ted T. Turner , Amos Hong-Kiat Leong
IPC分类号： G01R31/00 , G01R31/28 , G06F11/34 , G06Q20/34 , G06Q30/02 , G06Q30/04 , G07F7/00 , G07F7/02 , G07F17/00 , G06F15/20
CPC分类号： G07F7/02 , G01R31/2806 , G06F11/3438 , G06Q20/343 , G06Q30/0283 , G06Q30/04 , G07F17/00 , G07F17/0014 , G06F2201/88
摘要： A system and method for testing an electronic circuit is disclosed. The system includes a circuit board test platform having multiple electronic test capabilities, and a pay-per-use module that is coupled to the circuit board test platform. The pay-per-use module is adapted for monitoring use of the multiple electronic test capabilities of the circuit board test platform, and for debiting a number of usage credits from a usage credit pool based on the use of the multiple electronic test capabilities.
摘要翻译：公开了一种用于测试电子电路的系统和方法。该系统包括具有多个电子测试能力的电路板测试平台和耦合到电路板测试平台的按需付费模块。每用户付费模块适用于监视电路板测试平台的多个电子测试能力的使用，并且基于使用多个电子测试能力从使用信用库中借记一些使用信用。

5. 发明授权

US06233706B1 Method and apparatus for limited access circuit test 失效
标题翻译：有限接入电路测试方法和装置
公开(公告)号：US06233706B1
公开(公告)日：2001-05-15
申请号：US09169320
申请日：1998-10-09
申请人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , John E. McDermid , Kay C . Lannen
发明人： Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , John E. McDermid , Kay C . Lannen
IPC分类号： G01R3128
CPC分类号： G01R31/2801 , G01R31/2846
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

6. 发明授权

US5581463A Pay-per-use access to multiple electronic test capabilities and tester resources 失效
标题翻译：按用户可以使用多种电子测试功能和测试人员资源
公开(公告)号：US5581463A
公开(公告)日：1996-12-03
申请号：US195435
申请日：1994-02-14
申请人： Amanda L. Constant , David W. Webb , Sharon E. LaTourrette , Jeffrey C. Myers , Katherine Z. Withers-Miklos , Kay C. Lannen , Ted T. Turner , Amos H. Leong
发明人： Amanda L. Constant , David W. Webb , Sharon E. LaTourrette , Jeffrey C. Myers , Katherine Z. Withers-Miklos , Kay C. Lannen , Ted T. Turner , Amos H. Leong
IPC分类号： G01R31/00 , G01R31/28 , G06F11/34 , G06Q30/00 , G07F7/00 , G07F7/02 , G07F17/00 , G07B15/00
CPC分类号： G07F7/02 , G01R31/2801 , G01R31/2806 , G06F11/3438 , G06Q20/343 , G06Q30/0283 , G06Q30/04 , G07F17/00 , G07F17/0014 , G06F2201/88
摘要： A system and method for testing an electronic circuit is disclosed. The system includes a circuit board test platform having multiple electronic test capabilities and multiple hardware resources, and a pay-per-use module that is coupled to the circuit board test platform. The pay-per-use module is adapted for monitoring use of the multiple electronic test capabilities and the hardware resources of the circuit board test platform, and for debiting a number of usage credits from a usage credit pool based on the use of the multiple electronic test capabilities and the tester hardware resources.
摘要翻译：公开了一种用于测试电子电路的系统和方法。该系统包括具有多个电子测试能力和多个硬件资源的电路板测试平台，以及耦合到电路板测试平台的按需付费模块。每用户付费模块适用于监控多个电子测试能力和电路板测试平台的硬件资源的使用，并且用于根据使用多个电子邮件从使用信用卡借记多个使用信用测试功能和测试仪硬件资源。

7. 发明授权

US5481463A Pay-per-use access to multiple electronic test capabilities 失效
公开(公告)号：US5481463A
公开(公告)日：1996-01-02
申请号：US388765
申请日：1995-02-15
申请人： Amanda L. Constant , David W. Webb , Katherine Z. Withers-Miklos , Kay C. Lannen , Ted T. Turner , Amos H.-K. Leong
发明人： Amanda L. Constant , David W. Webb , Katherine Z. Withers-Miklos , Kay C. Lannen , Ted T. Turner , Amos H.-K. Leong
IPC分类号： G01R31/00 , G01R31/28 , G06F11/34 , G06Q20/34 , G06Q30/02 , G06Q30/04 , G07F7/00 , G07F7/02 , G07F17/00 , G07B15/00
CPC分类号： G07F7/02 , G01R31/2806 , G06F11/3438 , G06Q20/343 , G06Q30/0283 , G06Q30/04 , G07F17/00 , G07F17/0014 , G06F2201/88
摘要： A system and method for testing an electronic circuit is disclosed. The system includes a circuit board test platform having multiple electronic test capabilities, and a pay-per-use module that is coupled to the circuit board test platform. The pay-per-use module is adapted for monitoring use of the multiple electronic test capabilities of the circuit board test platform, and for debiting a number of usage credits from a usage credit pool based on the use of the multiple electronic test capabilities.

8. 发明授权

US5262716A Tester calibration procedure which includes fixturing 失效
标题翻译：测试仪校准程序，包括固定
公开(公告)号：US5262716A
公开(公告)日：1993-11-16
申请号：US871430
申请日：1992-04-21
申请人： Walter L. Gregory, Jr. , Jay M. Stepleton , Davis M. Glasgow , Kay C. Lannen
发明人： Walter L. Gregory, Jr. , Jay M. Stepleton , Davis M. Glasgow , Kay C. Lannen
IPC分类号： G01R31/319 , G01R35/00 , G01R31/02
CPC分类号： G01R31/31905 , G01R31/3191 , G01R35/00
摘要： A system and method for calibrating testers. A reference timing signal and an internal timing signal used in tester calibration are generated within a tester. A first calibration is performed wherein test module channel characteristics are measured and recorded, and an adjustment value is determined to correct the time placement of the internal timing signal. Driver and receiver delays are adjusted based on the characteristics measured in this first calibration, and the internal timing signal is adjusted as well. A second calibration is performed wherein temporal relationships between the adjusted internal timing signal and signals at the test module channel mint pins are determined. Driver and receiver delays are adjusted based on the results of this calibration. An optional calibration is performed wherein temporal relationship between the adjusted internal timing signal and signals at the board-interface end of a test fixture are measured. Using these measurements and the measurements obtained in the second calibration, a test fixture characterization is performed and recorded. Delays of the drivers and receivers are again adjusted to account for the fixture characteristics. Additional calibration methods provided by the present invention include a manual multi-module calibration to keep test module channels aligned when a new module is designated as the master module, and a manual synchronization clock calibration to deskew drivers and receivers relative to an external clock supplied by the device under test.

9. 发明授权

US06266787B1 Method and apparatus for selecting stimulus locations during limited access circuit test 失效
标题翻译：用于在受限访问电路测试期间选择刺激位置的方法和装置
公开(公告)号：US06266787B1
公开(公告)日：2001-07-24
申请号：US09169597
申请日：1998-10-09
申请人： John E. McDermid , Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , Kay C. Lannen
发明人： John E. McDermid , Cherif Ahrikencheikh , Rodney A. Browen , William P. Darbie , Kay C. Lannen
IPC分类号： G05B19048
CPC分类号： G01R31/27
摘要： A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.
摘要翻译：公开了一种系统，可以测试在电路板上具有公差的各个组件，而无需完全访问电路板上的每个节点。该系统使用从板的模型，组件公差和可访问节点列表开发测试限制的方法。还公开了通过限制所考虑的部件的数量来降低测试问题的复杂性的方法。还公开了通过限制所考虑的节点的数量来降低测试问题的复杂性的方法。还公开了一种将节点应用到板上的方法。最后，公开了一种校正与测试仪硬件有关的某些寄生效应的方法。

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